1 ? february 2003 hip4083 80v, 300ma three phase high side driver the hip4083 is a three phase high side n-channel mosfet driver, specifically targeted for pwm motor control. two hip4083 may be used together for 3 phase full bridge applications (see application block diagram). alternatively, the lower gates may be controlled directly from a buffered microprocessor output. unlike other members of the hip408x family, the hip4083 has no built in turn-on delay. each output (aho, bho, and cho) will turn-on 65ns after its input is switched low. likewise, each output will turn-off 60ns after its input is switched high. very short and very long dead times are possible when two hip4083 are used to drive a full bridge. this dead time is controlled by the input signal timing. the hip4083 does not have a built in charge pump. therefore, the bootstrap capacito rs must be recharged on a periodic basis by initiating a short refresh pulse. in most bridge applications, this will happen automatically every time the lower fets turn-on and the upper fets turn-off. however, it is still possible to use the hip4083 in applications that require the high side fets to be on for extended periods of time. this can be easily accomplished by sending a short refresh pulse to the dis pin. the hip4083 has reduced drive current compared to the hip4086 making it ideal for low to moderate power applications. the hip4083 is optimized for applications where size and cost are important. for high power applications driving large power fets, the hip4086 is recommended. features independently drives three high side n-channel mosfets in three phase bridge configuration bootstrap supply max voltage to 95vdc bias supply operation from 7v to 15v drives 1000pf load with typical rise times of 35ns and fall times of 30ns cmos/ttl compatible inputs programmable undervoltage protection applications brushless motors high side switches ac motor drives switched reluctance motor drives pinout ordering information part number temp. range ( o c) package pkg. no. hip4083ab -40 to 105 16 ld soic m16.15 hip4083ap -40 to 105 16 ld pdip e16.3 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 ahi bhi chi dis aho v ss bhb chs cho uvlo v dd ahs ahb bho chb bhs hip4083 (pdip, soic) top view data sheet fn4223.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 application block diagram functional block diagram 12v 80v gnd gnd ahi bhi chi aho bho cho hip4083 12v gnd ahi bhi chi aho bho cho micro- controller (optional) hip4083 chi bhi v dd dis ahb aho ahs uv 3 4 ahi 1 2 13 uvlo 12 level shifter driver 6 7 8 ahb aho ahs uv driver 6 8 ahb aho ahs uv driver 6 7 8 level shifter 7 level shifter logic en undervoltage detector uv hip4083
3 typical application: three phase bridge driver with programmable dead time truth table input output ahi , bhi , chi uv dis aho, bho, cho x1x0 xx1 0 1000 0001 note: x signifies that input can be either a ?1? or ?0?. power bus ahi bhi v ss chi dis ahb chb chs uvlo cho v dd bho bhs 4 3 2 1 6 5 8 7 ahs 9 13 10 11 16 12 15 14 bhb aho chip supply c bypass c bs c bs c bs optional microprocessor inputs optional microprocessor inputs oc sense 3-phase load ahi bhi v ss chi dis ahb chb chs uvlo cho v dd bho bhs 4 3 2 1 6 5 8 7 ahs 9 13 10 11 16 12 15 14 bhb aho r current sense hip4083 hip4083
4 typical application: high side switch 80v hip4083 12v gnd ahi bhi chi aho bho cho dis refresh micro- processor boot strap capacitor and diode required light pin descriptions pin number symbol description 6 11 16 ahb bhb chb (xhb) gate driver supplies. one external bootstrap diode and one capacitor are required fo r each. the bootstrap diode and capacitor may be omitted when the hip4083 is used to drive the lower gates in three phase full bridge applications. in this case, ti e all three xhb pins to v dd and tie the xhs pins to the sources of the lower fets. in full bridge applications, the lower fets must be turned on first at start up to refresh the bootstrap capacitors. in high side switch applications, the load will keep xhs lo w and refresh should happen automatically at start up. 1 2 3 ahi bhi chi (xhi ) logic level inputs. logic at these thr ee pins controls the three output drivers, aho, bho and cho. when xhi is low, xho is high. when xhi is high, xho is low. dis (disab le) overrides all input signals. xhi can be driven by signal levels of 0v to 15v (no greater than v dd ). 5v ss chip ground. 13 uvlo undervoltage setting. a resistor can be connected between this pin and v ss to program the under voltage set point - see figure 7. with this pin not connected the undervoltage set point is typically 7v. when this pin is tied to v dd , the undervoltage set point is typically 6.2v. 4 dis disable input. logic level input that when taken high sets all three outputs low. dis hi gh overrides all other inputs. when dis is taken low the outputs are controlled by the ot her inputs. dis can be driven by signal levels of 0v to 15v (no greater than v dd ). 7 10 15 aho bho cho (xho) gate connections. connect to the gates of the power mosfets in each phase. 8 9 14 ahs bhs chs (xhs) mosfet source connection. connect the sources of the power mosfets and the negative side of the bootstrap capacitors to these pins. in high side switch applications, 2ma of current will flow out of these pins into the load when the upper fets are off. this current is necessary to guarantee that the upper fets stay off. this current tends to pull xhs high. for proper refresh, the load mu st pull the voltage on xhs down to at least 7v below v dd . for example, when v dd = 12v, xhs must be pulled down to 5v. therefore, the minimum load necessary for proper refresh is given by the following equation: r min = 5v/2ma = 2.5k ? . so in this case, if the load has an impedance less than 5k ? , refresh will happen automatically at start up. 12 v dd positive supply rail. bypass this pin to v ss with a capacitor > 1 f. in applications where the bus voltage and chip v dd are at the same potential, it is a good idea to run a separate line from the supply to each. this greatly simplifies the filtering requirements. hip4083 hip4083
5 absolute maximum ratings t a =25 o c thermal information supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 16v logic i/o voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v voltage on xhs . . . . . . . . . -6v (transient) to 85v (-40 o c to 150 o c) voltage on xhb . . . . . . . . . . . . . . . . . . . . v xhs -0.3v to v xhs +v dd voltage on xlo . . . . . . . . . . . . . . . . . . . . . v ss -0.3v to v dd +0.3v voltage on xho . . . . . . . . . . . . . . . . . . . . v xhs -0.3v to v xhb +0.3v phase slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v/ns operating conditions supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v to +15v voltage on xhs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 80v voltage on xhb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v xhs +v dd operating ambient temperature range . . . . . . . . . -40 o c to 125 o c thermal resistance (typical, note 1) ja ( o c/w) soic package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 dip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum rating s? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on an evaluation pc board in free air. 2. all voltages are relative to v ss unless otherwise specified. 3. x = a, b and c. for example, xhs refers to ahs, bhs and chs. electrical specifications v dd = v xhb = 12v, v ss = v xhs = 0v, gate capacitance (c gate ) = 1000pf, r uv = parameter test conditions t j = 25 o c t j = -40 o c to 150 o c units min typ max min max supply currents and under voltage protection v dd quiescent current xhi = 5v 0.5 1.5 2.25 0.25 2.3 ma v dd operating current f = 20khz, 50% duty cycle 1.0 2.0 2.5 0.75 3.0 ma xhb on quiescent current xhi = 0v 65 100 240 45 250 a xhb off quiescent current xhi = 5v 0.6 0.85 1.3 0.5 1.4 ma xhb operating current f = 20khz, 50% duty cycle 0.6 0.85 1.2 0.5 1.3 ma v dd rising undervoltage threshold r uv open 6.2 7.0 8.0 6.1 8.1 v v dd falling undervoltage threshold r uv open 5.75 6.5 7.5 5.25 7.6 v minimum undervoltage threshold r uv = v dd 5.0 6.2 6.9 4.5 7.0 v input pins: ahi, bhi, chi and dis low level input voltage - - 1.0 - 0.8 v high level input voltage 2.5 - - 2.7 - v input voltage hysteresis - 35 - - - mv low level input current v in = 0v -145 -100 -60 -150 -50 a high level input current v in = 5v -1 - +1 -10 +10 a gate driver output pins: aho, bho, and cho average turn-on current v out 0v to 5v 100 240 400 50 500 ma average turn-off current v out v dd to 4v 150 300 450 100 550 ma hip4083 hip4083
6 switching specifications v dd = v xhb = 12v, v ss = v xhs = 0v, c gate = 1000pf parameter test conditions t j = 25 o c t js = -40 o c to 150 o c units min typ max min max turn-off propagation delay (xhi - xho) no load - 60 80 90 ns turn-on propagation delay (xhi - xho) no load - 65 90 100 ns rise time (10 - 90%) c gate = 1000pf - 35 60 - 65 ns fall time (90 - 10%) c gate = 1000pf - 30 50 - 55 ns disable turn-off propagation delay no load - 65 - - 100 ns disable to output enable (dis - xho) no load - 70 - - 100 ns typical performance curves figure 1. v dd supply current vs v dd supply voltage figure 2. v dd supply current vs switching frequency figure 3. floating supply off bias current figure 4. floating supply on bias current -60 -40 -20 0 20 40 60 80 100 120 140 160 1.0 1.2 1.4 1.6 1.8 2.0 junction temperature ( o c) v dd supply current (ma) v dd = 16v v dd = 15v v dd = 12v v dd = 10v v dd = 8v v dd = 7v -60 -40 -20 0 20 40 60 80 100 120 140 160 3.0 3.5 4.0 4.5 junction temperature ( o c) v dd supply current (ma) 200khz 100khz 50khz 10khz 20khz -60 -40 -20 0 20 40 60 80 100 120 140 160 650 700 750 800 850 900 950 junction temperature ( o c) xhb supply off current ( a) (v xhb - v xhs ) = 15v (v xhb - v xhs ) = 14v (v xhb - v xhs ) = 10v (v xhb - v xhs ) = 8v (v xhb - v xhs ) = 7v (v xhb - v xhs ) = 13v (v xhb - v xhs ) = 12v -60 -40 -20 0 20 40 60 80 100 120 140 160 60 70 80 90 100 110 120 junction temperature ( o c) xhb on supply current ( a) (v xhb - v xhs ) = 15v (v xhb - v xhs ) = 12v (v xhb - v xhs ) = 10v (v xhb - v xhs ) = 8v (v xhb - v xhs ) = 7v hip4083 hip4083
7 figure 5. floating supply switching bias current f igure 6. floating supply switching bias current figure 7. undervoltage threshold figure 8. propagation delay figure 9. rise and fall time (10-90%) figure 10. gate driver average turn-on current typical performance curves (continued) -60 -40 -20 0 20 40 60 80 100 120 140 160 0 1 2 3 4 junction temperature ( o c) xhb supply current (ma) c gate = 1000pf 200khz 100khz 50khz 20khz 10khz -60 -40 -20 0 20 40 60 80 100 120 140 160 0 0.5 1.0 1.5 2.0 2.5 junction temperature ( o c) xhb supply current (ma) no load 200khz 100khz 50khz 20khz 10khz -60 -40 -20 0 20 40 60 80 100 120 140 160 5 6 7 8 9 10 junction temperature ( o c) undervoltage shutdown/enable enable (50k, uvlo to gnd) trip (50k, uvlo to gnd) enable (uvlo open) trip (uvlo open) trip/enable (ok, uvlo to v dd ) voltage (v) -60 -40 -20 0 20 40 60 80 100 120 140 160 40 60 80 100 junction temperature ( o c) propagation delay (ns) turn-off turn-on enable turn-on disable turn-off -60 -40 -20 0 20 40 60 80 100 120 140 160 20 30 40 50 junction temperature ( o c) rise and fall time (ns) turn-on turn-off c gate = 1000pf -60 -40 -20 0 20 40 60 80 100 120 140 160 0.1 0.15 0.2 0.25 0.3 0.35 junction temperature ( o c) average turn-on current (a) 0v to 5v 15v 12v 10v 8v 7v hip4083 hip4083
8 figure 11. gate driver average turn-off current figure 12. high voltage leakage current typical performance curves (continued) -60 -40 -20 0 20 40 60 80 100 120 140 160 0 0.1 0.2 0.3 0.4 0.5 junction temperature ( o c) average turn-off current (a) v dd to 4v 15v 12v 10v 8v 7v -60 -40 -20 0 20 40 60 80 100 120 140 160 0 10 20 30 40 50 junction temperature ( o c) xhs leakage current ( a) hip4083 hip4083
9 hip4083 notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo se ries symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or prot rusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendicular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m b s e a -c- dual-in-line plastic packages (pdip) e16.3 (jedec ms-001-bb issue d) 16 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n16 169 rev. 0 12/93 hip4083
10 all intersil u.s. products are manufactured, asse mbled and tested utilizin g iso9000 quality systems. intersil corporation?s quality certifications c an be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com hip4083 notes: 1. symbols are defined in the ?mo se ries symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optiona l. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are sh own for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m small outline plastic packages (soic) m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3859 0.3937 9.80 10.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 0 o 8 o 0 o 8 o - rev. 0 12/93 hip4083
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